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DTCO exploration for efficient standard cell power rails

dc.contributor.authorChava, Bharani
dc.contributor.authorRyckaert, Julien
dc.contributor.authorMattii, Luca
dc.contributor.authorSherazi, Yasser
dc.contributor.authorDebacker, Peter
dc.contributor.authorSpessot, Alessio
dc.contributor.authorVerkest, Diederik
dc.date.accessioned2021-10-25T17:09:44Z
dc.date.available2021-10-25T17:09:44Z
dc.date.issued2018
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/30393
dc.sourceIIOimport
dc.titleDTCO exploration for efficient standard cell power rails
dc.typeProceedings paper
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.imecauthorSherazi, Yasser
dc.contributor.imecauthorDebacker, Peter
dc.contributor.imecauthorSpessot, Alessio
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.orcidimecDebacker, Peter::0000-0003-3825-5554
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage105880B
dc.source.conferenceDesign-Process-Technology Co-optimization for Manufacturability XII
dc.source.conferencedate25/02/2018
dc.source.conferencelocationSan Jose, CA USA
dc.identifier.urlhttps://doi.org/10.1117/12.2293500
imec.availabilityPublished - open access
imec.internalnotesProceedings of SPIE; Vol. 10588


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