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Feasibility of 250 nm gate patterning using i-line with OPC

dc.contributor.authorVan Driessche, Veerle
dc.contributor.authorFinders, Jo
dc.contributor.authorTritchkov, Alexander
dc.contributor.authorRonse, Kurt
dc.contributor.authorVan den hove, Luc
dc.contributor.authorTzviatkov, Plamen
dc.date.accessioned2021-10-01T09:16:05Z
dc.date.available2021-10-01T09:16:05Z
dc.date.issued1998
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/3039
dc.sourceIIOimport
dc.titleFeasibility of 250 nm gate patterning using i-line with OPC
dc.typeJournal article
dc.contributor.imecauthorVan Driessche, Veerle
dc.contributor.imecauthorRonse, Kurt
dc.contributor.imecauthorVan den hove, Luc
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage111
dc.source.endpage116
dc.source.journalMicroelectronic Engineering
dc.source.volume41/42
imec.availabilityPublished - open access
imec.internalnotesMNE'97. 15-18 Sept. 1997; Athens, Greece


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