From confined area to wafer level nanotopography metrology solution for process developments
dc.contributor.author | Kim, Tae-Gon | |
dc.date.accessioned | 2021-10-25T21:03:39Z | |
dc.date.available | 2021-10-25T21:03:39Z | |
dc.date.issued | 2018 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/31059 | |
dc.source | IIOimport | |
dc.title | From confined area to wafer level nanotopography metrology solution for process developments | |
dc.type | Meeting abstract | |
dc.source.peerreview | no | |
dc.source.conference | China Semiconductor Technology International Conference (CSTIC) Symposium V: CMP and Post-Polish Cleaning | |
dc.source.conferencedate | 11/03/2018 | |
dc.source.conferencelocation | Shanghai China | |
dc.identifier.url | https://www.semiconchina.org/en/725 | |
imec.availability | Published - imec |
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