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Consideration of UFET architecture for the 5nm node and beyond logic transistor

dc.contributor.authorKumar Das, Uttam
dc.contributor.authorEneman, Geert
dc.contributor.authorVelampati, Ravi
dc.contributor.authorChauhan, Y.
dc.contributor.authorJinesh, K.
dc.contributor.authorBhattacharya, T.
dc.date.accessioned2021-10-25T21:19:16Z
dc.date.available2021-10-25T21:19:16Z
dc.date.issued2018
dc.identifier.issn2168-6734
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/31092
dc.sourceIIOimport
dc.titleConsideration of UFET architecture for the 5nm node and beyond logic transistor
dc.typeJournal article
dc.contributor.imecauthorEneman, Geert
dc.contributor.orcidimecEneman, Geert::0000-0002-5849-3384
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage1129
dc.source.endpage1135
dc.source.journalIEEE Journal of the Electron Devices Society
dc.source.volume6
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8466575
imec.availabilityPublished - open access


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