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Enabling CMOS scaling towards 3nm and beyond

dc.contributor.authorMocuta, Anda
dc.contributor.authorWeckx, Pieter
dc.contributor.authorDemuynck, Steven
dc.contributor.authorRadisic, Alex
dc.contributor.authorOniki, Yusuke
dc.contributor.authorRyckaert, Julien
dc.date.accessioned2021-10-25T23:34:17Z
dc.date.available2021-10-25T23:34:17Z
dc.date.issued2018
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/31354
dc.sourceIIOimport
dc.titleEnabling CMOS scaling towards 3nm and beyond
dc.typeProceedings paper
dc.contributor.imecauthorWeckx, Pieter
dc.contributor.imecauthorDemuynck, Steven
dc.contributor.imecauthorRadisic, Alex
dc.contributor.imecauthorOniki, Yusuke
dc.contributor.imecauthorRyckaert, Julien
dc.contributor.orcidimecOniki, Yusuke::0000-0002-6619-1327
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage147
dc.source.endpage148
dc.source.conferenceIEEE Symposium on VLSI Technology
dc.source.conferencedate19/06/2018
dc.source.conferencelocationHonolulu, HI USA
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8510683
imec.availabilityPublished - open access


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