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Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks

dc.contributor.authorPerumkunnil, Manu
dc.contributor.authorOh, Hyungrock
dc.contributor.authorHartmann, Matthias
dc.contributor.authorSakhare, Sushil
dc.contributor.authorTenllado, Christian
dc.contributor.authorIgnacio Gomez, Jose
dc.contributor.authorKar, Gouri Sankar
dc.contributor.authorFurnemont, Arnaud
dc.contributor.authorCatthoor, Francky
dc.contributor.authorSenni, Sophiane
dc.contributor.authorNovo, David
dc.contributor.authorGamatie, Abdoulaye
dc.contributor.authorTorres, Lionel
dc.date.accessioned2021-10-26T01:03:25Z
dc.date.available2021-10-26T01:03:25Z
dc.date.issued2018
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/31512
dc.sourceIIOimport
dc.titleMain memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks
dc.typeProceedings paper
dc.contributor.imecauthorPerumkunnil, Manu
dc.contributor.imecauthorOh, Hyungrock
dc.contributor.imecauthorHartmann, Matthias
dc.contributor.imecauthorKar, Gouri Sankar
dc.contributor.imecauthorFurnemont, Arnaud
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecOh, Hyungrock::0000-0001-5244-5755
dc.contributor.orcidimecHartmann, Matthias::0000-0001-6248-1151
dc.contributor.orcidimecFurnemont, Arnaud::0000-0002-6378-1030
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.source.peerreviewyes
dc.source.beginpage103
dc.source.endpage108
dc.source.conference2018 Design, Automation & Test in Europe Conference & Exhibition - DATE
dc.source.conferencedate19/03/2018
dc.source.conferencelocationDresden Germany
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8341987
imec.availabilityPublished - imec


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