Design of a fully balanced ASIC coprocessor implementing complete addition formulas on Weierstrass
dc.contributor.author | Pirotte, Niels | |
dc.contributor.author | Vliegen, Jo | |
dc.contributor.author | Batina, Lej | |
dc.contributor.author | Mentens, Nele | |
dc.date.accessioned | 2021-10-26T01:15:53Z | |
dc.date.available | 2021-10-26T01:15:53Z | |
dc.date.issued | 2018 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/31534 | |
dc.source | IIOimport | |
dc.title | Design of a fully balanced ASIC coprocessor implementing complete addition formulas on Weierstrass | |
dc.type | Proceedings paper | |
dc.contributor.imecauthor | Mentens, Nele | |
dc.date.embargo | 9999-12-31 | |
dc.source.peerreview | yes | |
dc.source.beginpage | 1 | |
dc.source.endpage | 8 | |
dc.source.conference | 2018 21st Euromicro Conference on Digital System Design (DSD) | |
dc.source.conferencedate | 29/08/2018 | |
dc.source.conferencelocation | Prague Czech Republic | |
dc.identifier.url | https://ieeexplore.ieee.org/document/8491866 | |
imec.availability | Published - open access |