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Border trap based modeling of SiC transistor transfer characteristics

dc.contributor.authorTyaginov, Stanislav
dc.contributor.authorJech, Markus
dc.contributor.authorRzepa, Gerhard
dc.contributor.authorGrill, Alexander
dc.contributor.authorEl-Sayed, Al-Moatasem
dc.contributor.authorPobegen, Gregor
dc.contributor.authorMakarov, Alexander
dc.contributor.authorGrasser, Tibor
dc.date.accessioned2021-10-26T06:05:59Z
dc.date.available2021-10-26T06:05:59Z
dc.date.issued2018
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/31985
dc.sourceIIOimport
dc.titleBorder trap based modeling of SiC transistor transfer characteristics
dc.typeProceedings paper
dc.contributor.imecauthorTyaginov, Stanislav
dc.contributor.imecauthorGrill, Alexander
dc.contributor.orcidimecGrill, Alexander::0000-0003-1615-1033
dc.source.peerreviewyes
dc.source.beginpage1
dc.source.endpage5
dc.source.conferenceInternational Integrated Reliability Workshop (IIRW)
dc.source.conferencedate7/11/2018
dc.source.conferencelocationSouth Lake Tahoe, CA USA
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8727083
imec.availabilityPublished - imec


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