Show simple item record

Nemesis: Studying microarchitectural timing leaks in rudimentary CPU interrupt logic

dc.contributor.authorVan Bulck, Jo
dc.contributor.authorPiessens, Frank
dc.contributor.authorStrackx, Raoul
dc.date.accessioned2021-10-26T06:25:29Z
dc.date.available2021-10-26T06:25:29Z
dc.date.issued2018
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/32013
dc.sourceIIOimport
dc.titleNemesis: Studying microarchitectural timing leaks in rudimentary CPU interrupt logic
dc.typeProceedings paper
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage178
dc.source.endpage195
dc.source.conferenceCCS '18 Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security
dc.source.conferencedate15/10/2018
dc.source.conferencelocationtoronto Canada
dc.identifier.urlhttps://doi.org/10.1145/3243734.3243822
imec.availabilityPublished - open access


Files in this item

Thumbnail
Name:
42529.pdf
Size:
1.292Mb
Format:
PDF
View/open

This item appears in the following collection(s)

Show simple item record