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Trap-aware compact modeling and power-performance assessment of III-V tunnel FET

dc.contributor.authorXiang, Yang
dc.contributor.authorYakimets, Dmitry
dc.contributor.authorSant, Saurabh
dc.contributor.authorMemisevic, Elvedin
dc.contributor.authorGarcia Bardon, Marie
dc.contributor.authorVerhulst, Anne
dc.contributor.authorParvais, Bertrand
dc.contributor.authorSchenk, Andreas
dc.contributor.authorWernersson, Lars-Erik
dc.contributor.authorGroeseneken, Guido
dc.date.accessioned2021-10-26T09:47:55Z
dc.date.available2021-10-26T09:47:55Z
dc.date.issued2018-10
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/32298
dc.sourceIIOimport
dc.titleTrap-aware compact modeling and power-performance assessment of III-V tunnel FET
dc.typeProceedings paper
dc.contributor.imecauthorXiang, Yang
dc.contributor.imecauthorYakimets, Dmitry
dc.contributor.imecauthorGarcia Bardon, Marie
dc.contributor.imecauthorVerhulst, Anne
dc.contributor.imecauthorParvais, Bertrand
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.orcidimecXiang, Yang::0000-0003-0091-6935
dc.contributor.orcidimecVerhulst, Anne::0000-0002-3742-9017
dc.contributor.orcidimecParvais, Bertrand::0000-0003-0769-7069
dc.contributor.orcidimecGroeseneken, Guido::0000-0003-3763-2098
dc.source.peerreviewyes
dc.source.conference2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
dc.source.conferencedate15/10/2018
dc.source.conferencelocationBurlingame, CA The United States of America
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8640183
imec.availabilityPublished - imec


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