dc.contributor.author | Breuil, Laurent | |
dc.contributor.author | Nyns, Laura | |
dc.contributor.author | Banerjee, Kaustuv | |
dc.contributor.author | Vadakupudhu Palayam, Senthil | |
dc.contributor.author | Subirats, Alexandre | |
dc.contributor.author | Richard, Olivier | |
dc.contributor.author | Conard, Thierry | |
dc.contributor.author | Van den Bosch, Geert | |
dc.contributor.author | Furnemont, Arnaud | |
dc.date.accessioned | 2021-10-27T07:45:04Z | |
dc.date.available | 2021-10-27T07:45:04Z | |
dc.date.issued | 2019 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/32616 | |
dc.source | IIOimport | |
dc.title | Impact of SiON tunnel layer composition on 3D NAND cell performance | |
dc.type | Proceedings paper | |
dc.contributor.imecauthor | Breuil, Laurent | |
dc.contributor.imecauthor | Nyns, Laura | |
dc.contributor.imecauthor | Banerjee, Kaustuv | |
dc.contributor.imecauthor | Vadakupudhu Palayam, Senthil | |
dc.contributor.imecauthor | Richard, Olivier | |
dc.contributor.imecauthor | Conard, Thierry | |
dc.contributor.imecauthor | Van den Bosch, Geert | |
dc.contributor.imecauthor | Furnemont, Arnaud | |
dc.contributor.orcidimec | Breuil, Laurent::0000-0003-2869-1651 | |
dc.contributor.orcidimec | Nyns, Laura::0000-0001-8220-870X | |
dc.contributor.orcidimec | Banerjee, Kaustuv::0000-0001-8003-6211 | |
dc.contributor.orcidimec | Richard, Olivier::0000-0002-3994-8021 | |
dc.contributor.orcidimec | Conard, Thierry::0000-0002-4298-5851 | |
dc.contributor.orcidimec | Van den Bosch, Geert::0000-0001-9971-6954 | |
dc.contributor.orcidimec | Furnemont, Arnaud::0000-0002-6378-1030 | |
dc.source.peerreview | yes | |
dc.source.beginpage | 152 | |
dc.source.endpage | 155 | |
dc.source.conference | 2019 IEEE 11th International Memory Workshop (IMW) | |
dc.source.conferencedate | 12/05/2019 | |
dc.source.conferencelocation | Monterey, CA USA | |
dc.identifier.url | https://ieeexplore.ieee.org/document/8739714 | |
imec.availability | Published - imec | |