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dc.contributor.authorBreuil, Laurent
dc.contributor.authorNyns, Laura
dc.contributor.authorBanerjee, Kaustuv
dc.contributor.authorVadakupudhu Palayam, Senthil
dc.contributor.authorSubirats, Alexandre
dc.contributor.authorRichard, Olivier
dc.contributor.authorConard, Thierry
dc.contributor.authorVan den Bosch, Geert
dc.contributor.authorFurnemont, Arnaud
dc.date.accessioned2021-10-27T07:45:04Z
dc.date.available2021-10-27T07:45:04Z
dc.date.issued2019
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/32616
dc.sourceIIOimport
dc.titleImpact of SiON tunnel layer composition on 3D NAND cell performance
dc.typeProceedings paper
dc.contributor.imecauthorBreuil, Laurent
dc.contributor.imecauthorNyns, Laura
dc.contributor.imecauthorBanerjee, Kaustuv
dc.contributor.imecauthorVadakupudhu Palayam, Senthil
dc.contributor.imecauthorRichard, Olivier
dc.contributor.imecauthorConard, Thierry
dc.contributor.imecauthorVan den Bosch, Geert
dc.contributor.imecauthorFurnemont, Arnaud
dc.contributor.orcidimecBreuil, Laurent::0000-0003-2869-1651
dc.contributor.orcidimecNyns, Laura::0000-0001-8220-870X
dc.contributor.orcidimecBanerjee, Kaustuv::0000-0001-8003-6211
dc.contributor.orcidimecRichard, Olivier::0000-0002-3994-8021
dc.contributor.orcidimecConard, Thierry::0000-0002-4298-5851
dc.contributor.orcidimecVan den Bosch, Geert::0000-0001-9971-6954
dc.contributor.orcidimecFurnemont, Arnaud::0000-0002-6378-1030
dc.source.peerreviewyes
dc.source.beginpage152
dc.source.endpage155
dc.source.conference2019 IEEE 11th International Memory Workshop (IMW)
dc.source.conferencedate12/05/2019
dc.source.conferencelocationMonterey, CA USA
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8739714
imec.availabilityPublished - imec


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