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Dual-gate self-aligned a-InGaZnO transistor model for flexible circuit applications

dc.contributor.authorDe Roose, Florian
dc.contributor.authorCeliker, Hikmet
dc.contributor.authorGenoe, Jan
dc.contributor.authorDehaene, Wim
dc.contributor.authorMyny, Kris
dc.date.accessioned2021-10-27T08:31:45Z
dc.date.available2021-10-27T08:31:45Z
dc.date.issued2019
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/32829
dc.sourceIIOimport
dc.titleDual-gate self-aligned a-InGaZnO transistor model for flexible circuit applications
dc.typeProceedings paper
dc.contributor.imecauthorDe Roose, Florian
dc.contributor.imecauthorCeliker, Hikmet
dc.contributor.imecauthorGenoe, Jan
dc.contributor.imecauthorDehaene, Wim
dc.contributor.imecauthorMyny, Kris
dc.contributor.orcidimecDe Roose, Florian::0000-0003-4490-5007
dc.contributor.orcidimecGenoe, Jan::0000-0002-4019-5979
dc.contributor.orcidimecMyny, Kris::0000-0002-5230-495X
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage25
dc.source.endpage29
dc.source.conferenceDesign, Automation and Test in Europe Conference - DATE
dc.source.conferencedate25/03/2019
dc.source.conferencelocationFlorence Italy
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8715075
imec.availabilityPublished - open access


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