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Two-stage voltage amplifier design based on experimental Line-Tunnel FET data

dc.contributor.authorFilho, Walter Goncalez
dc.contributor.authorMartino, J.A.
dc.contributor.authorRangel, Roberto
dc.contributor.authorSimoen, Eddy
dc.contributor.authorAgopian, P.G.D.
dc.contributor.authorRooyackers, Rita
dc.contributor.authorClaeys, Cor
dc.contributor.authorCollaert, Nadine
dc.date.accessioned2021-10-27T09:14:00Z
dc.date.available2021-10-27T09:14:00Z
dc.date.issued2019
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/32965
dc.sourceIIOimport
dc.titleTwo-stage voltage amplifier design based on experimental Line-Tunnel FET data
dc.typeProceedings paper
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.source.peerreviewyes
dc.source.conferenceS3S - IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
dc.source.conferencedate14/10/2019
dc.source.conferencelocationSan Jose, CA USA
imec.availabilityPublished - imec


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