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dc.contributor.authorFranco, Jacopo
dc.contributor.authorWu, Zhicheng
dc.contributor.authorRzepa, Gerhard
dc.contributor.authorVandooren, Anne
dc.contributor.authorArimura, Hiroaki
dc.contributor.authorClaes, Dieter
dc.contributor.authorHoriguchi, Naoto
dc.contributor.authorCollaert, Nadine
dc.contributor.authorLinten, Dimitri
dc.contributor.authorGrasser, Tibor
dc.contributor.authorKaczer, Ben
dc.date.accessioned2021-10-27T09:18:44Z
dc.date.available2021-10-27T09:18:44Z
dc.date.issued2019-12
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/32978
dc.sourceIIOimport
dc.titleLow thermal budget dual-dipole gate stacks engineered for sufficient BTI reliability in novel integration schemes
dc.typeProceedings paper
dc.contributor.imecauthorFranco, Jacopo
dc.contributor.imecauthorWu, Zhicheng
dc.contributor.imecauthorVandooren, Anne
dc.contributor.imecauthorArimura, Hiroaki
dc.contributor.imecauthorClaes, Dieter
dc.contributor.imecauthorHoriguchi, Naoto
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorLinten, Dimitri
dc.contributor.imecauthorKaczer, Ben
dc.contributor.orcidimecFranco, Jacopo::0000-0002-7382-8605
dc.contributor.orcidimecVandooren, Anne::0000-0002-2412-0176
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.contributor.orcidimecLinten, Dimitri::0000-0001-8434-1838
dc.contributor.orcidimecKaczer, Ben::0000-0002-1484-4007
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage215
dc.source.endpage216
dc.source.conferenceIEEE Electron Devices Technology and Manufacturing (EDTM) Conference 2019
dc.source.conferencedate12/03/2019
dc.source.conferencelocationSingapore Singapore
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8731237
imec.availabilityPublished - open access


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