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Test and debug strategy for TSMC CoWoS stacking process-based heterogeneous 3D-IC: A silicon study
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Test and debug strategy for TSMC CoWoS stacking process-based heterogeneous 3D-IC: A silicon study
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Date
2019
Book Chapter
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APA
Chicago
Harvard
IEEE
Basic data
APA
Chicago
Harvard
IEEE
Author(s)
Goel, Sandeep K.
;
Adham, Saman
;
Wang, Min-Jer
;
Lee, Frank
;
Chickermane, Vivek
;
Keller, Brion
;
Valind, Thomas
;
Marinissen, Erik Jan
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2002
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Acq. date: 2026-08-04
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Views
2002
since deposited on 2021-10-27
1
last month
Acq. date: 2026-08-04
Citations