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Test and debug strategy for TSMC CoWoS stacking process-based heterogeneous 3D-IC: A silicon study

dc.contributor.authorGoel, Sandeep K.
dc.contributor.authorAdham, Saman
dc.contributor.authorWang, Min-Jer
dc.contributor.authorLee, Frank
dc.contributor.authorChickermane, Vivek
dc.contributor.authorKeller, Brion
dc.contributor.authorValind, Thomas
dc.contributor.authorMarinissen, Erik Jan
dc.date.accessioned2021-10-27T09:38:59Z
dc.date.available2021-10-27T09:38:59Z
dc.date.issued2019-03
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/33033
dc.sourceIIOimport
dc.titleTest and debug strategy for TSMC CoWoS stacking process-based heterogeneous 3D-IC: A silicon study
dc.typeBook chapter
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewyes
dc.source.beginpage325
dc.source.bookHandbook of 3D Integration - Volume 4: 3D Design, Test, and Thermal Management
dc.source.endpage346
dc.identifier.urlhttps://doi.org/10.1002/9783527697052.ch15
imec.availabilityPublished - imec


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