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A novel reconfigurable hardware architecture of neural network

dc.contributor.authorKhalil, K.
dc.contributor.authorEldash, O.
dc.contributor.authorDey, Bappaditya
dc.contributor.authorKumar, A.
dc.contributor.authorBayoumi, M.
dc.date.accessioned2021-10-27T11:20:26Z
dc.date.available2021-10-27T11:20:26Z
dc.date.issued2019
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/33277
dc.sourceIIOimport
dc.titleA novel reconfigurable hardware architecture of neural network
dc.typeProceedings paper
dc.contributor.imecauthorDey, Bappaditya
dc.contributor.orcidimecDey, Bappaditya::0000-0002-0886-137X
dc.source.peerreviewyes
dc.source.conference2019 IEEE 62nd International Midwest Symposium on Circuits and Systems
dc.source.conferencedate4/08/2019
dc.source.conferencelocationDallas, TX USA
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8884809
imec.availabilityPublished - imec


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