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A power-efficient architecture for on-chip reservoir computing

dc.contributor.authorSackesyn, Stijn
dc.contributor.authorMa, Chonghuai
dc.contributor.authorKatumba, Andrew
dc.contributor.authorDambre, Joni
dc.contributor.authorBienstman, Peter
dc.date.accessioned2021-10-27T17:24:11Z
dc.date.available2021-10-27T17:24:11Z
dc.date.issued2019
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/33921
dc.sourceIIOimport
dc.titleA power-efficient architecture for on-chip reservoir computing
dc.typeProceedings paper
dc.contributor.imecauthorSackesyn, Stijn
dc.contributor.imecauthorMa, Chonghuai
dc.contributor.imecauthorDambre, Joni
dc.contributor.imecauthorBienstman, Peter
dc.contributor.orcidimecBienstman, Peter::0000-0001-6259-464X
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage161
dc.source.endpage164
dc.source.conferenceArtificial Neural Networks and Machine Learning - ICANN 2019
dc.source.conferencedate17/09/2019
dc.source.conferencelocationMunich Germany
dc.identifier.urlhttps://doi.org/10.1007/978-3-030-30493-5_16
imec.availabilityPublished - open access
imec.internalnotesLecture Notes in Computer Science; Vol. LNCS 11731


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