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Optimization of read and write performance of SRAMs for node 5nm and beyond

dc.contributor.authorShaik, Khaja Ahmad
dc.contributor.authorGupta, Mohit
dc.contributor.authorWeckx, Pieter
dc.contributor.authorSpessot, Alessio
dc.date.accessioned2021-10-27T17:58:30Z
dc.date.available2021-10-27T17:58:30Z
dc.date.issued2019
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/33974
dc.sourceIIOimport
dc.titleOptimization of read and write performance of SRAMs for node 5nm and beyond
dc.typeProceedings paper
dc.contributor.imecauthorGupta, Mohit
dc.contributor.imecauthorWeckx, Pieter
dc.contributor.imecauthorSpessot, Alessio
dc.contributor.orcidimecGupta, Mohit::0000-0002-1924-1264
dc.source.peerreviewyes
dc.source.beginpage1096203
dc.source.conferenceDesign-Process-Technology Co-optimization for Manufacturability XIII
dc.source.conferencedate24/02/2019
dc.source.conferencelocationSan Jose, CA USA
dc.identifier.urlhttps://doi.org/10.1117/12.2515162
imec.availabilityPublished - imec
imec.internalnotesProceedings of SPIE; Vol. 10962


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