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Impact of device architecture and gate stack processing on the low-frequency noise of silicon nanowire transistors

dc.contributor.authorSimoen, Eddy
dc.contributor.authorOliveira, Alberto Vinicius
dc.contributor.authorVeloso, Anabela
dc.contributor.authorVaisman Chasin, Adrian
dc.contributor.authorRitzenthaler, Romain
dc.contributor.authorMertens, Hans
dc.contributor.authorHoriguchi, Naoto
dc.contributor.authorClaeys, Cor
dc.date.accessioned2021-10-27T18:22:23Z
dc.date.available2021-10-27T18:22:23Z
dc.date.issued2019
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/34009
dc.sourceIIOimport
dc.titleImpact of device architecture and gate stack processing on the low-frequency noise of silicon nanowire transistors
dc.typeProceedings paper
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.imecauthorVaisman Chasin, Adrian
dc.contributor.imecauthorRitzenthaler, Romain
dc.contributor.imecauthorMertens, Hans
dc.contributor.imecauthorHoriguchi, Naoto
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.contributor.orcidimecVaisman Chasin, Adrian::0000-0002-9940-0260
dc.contributor.orcidimecRitzenthaler, Romain::0000-0002-8615-3272
dc.contributor.orcidimecHoriguchi, Naoto::0000-0001-5490-0416
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage1
dc.source.endpage4
dc.source.conference2019 IEEE 13th International Conference on ASIC (ASICON)
dc.source.conferencedate29/10/2019
dc.source.conferencelocationChongqing China
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8983679
imec.availabilityPublished - open access


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