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Wafer alignment mark placement accuracy impact on the layer to layer overlay performance

dc.contributor.authorvan Haren, Richard
dc.contributor.authorSteinert, Steffen
dc.contributor.authorMouraille, Orion
dc.contributor.authorD'have, Koen
dc.contributor.authorVan Dijk, Leon
dc.contributor.authorHermans, Jan
dc.contributor.authorBeyer, Dirk
dc.date.accessioned2021-10-27T20:56:19Z
dc.date.available2021-10-27T20:56:19Z
dc.date.issued2019
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/34233
dc.sourceIIOimport
dc.titleWafer alignment mark placement accuracy impact on the layer to layer overlay performance
dc.typeProceedings paper
dc.contributor.imecauthorvan Haren, Richard
dc.contributor.imecauthorD'have, Koen
dc.contributor.imecauthorHermans, Jan
dc.contributor.orcidimecD'have, Koen::0000-0002-5195-9241
dc.contributor.orcidimecHermans, Jan::0000-0003-1249-8902
dc.source.peerreviewyes
dc.source.beginpage1114811
dc.source.conferencePhotomask Technology 2019
dc.source.conferencedate15/09/2019
dc.source.conferencelocationMonterey, CA USA
dc.identifier.urlhttps://doi.org/10.1117/12.2536270
imec.availabilityPublished - imec
imec.internalnotesProceedings of SPIE; Vol. 11148


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