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Evolvable hardware architectures on FPGA for side-channel security

dc.contributor.authorLabafnya, M.
dc.contributor.authorEtemadi Borujeni, S.
dc.contributor.authorMentens, N.
dc.date.accessioned2021-10-28T23:36:07Z
dc.date.available2021-10-28T23:36:07Z
dc.date.issued2020
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/35427
dc.sourceIIOimport
dc.titleEvolvable hardware architectures on FPGA for side-channel security
dc.typeProceedings paper
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.conferenceApplied Cryptography and Network Security Workshops - ACNS Workshop on Artificial Intelligence in Hardware Security
dc.source.conferencedate19/10/2020
dc.source.conferencelocationRome Italy
imec.availabilityPublished - open access


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