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Gate stack optimisation for advanced CMOS process

dc.contributor.authorKubicek, Stefan
dc.contributor.authorVandenberghe, Geert
dc.contributor.authorSchaekers, Marc
dc.contributor.authorKol'dyaev, Victor
dc.contributor.authorJansen, Philippe
dc.contributor.authorBadenes, Gonçal
dc.contributor.authorDeferm, Ludo
dc.contributor.authorDe Meyer, Kristin
dc.contributor.authorKerr, Daniel
dc.contributor.authorNaem, Abdalla
dc.date.accessioned2021-10-06T11:34:48Z
dc.date.available2021-10-06T11:34:48Z
dc.date.issued1999
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/3578
dc.sourceIIOimport
dc.titleGate stack optimisation for advanced CMOS process
dc.typeProceedings paper
dc.contributor.imecauthorKubicek, Stefan
dc.contributor.imecauthorVandenberghe, Geert
dc.contributor.imecauthorSchaekers, Marc
dc.contributor.imecauthorDeferm, Ludo
dc.contributor.imecauthorDe Meyer, Kristin
dc.contributor.orcidimecSchaekers, Marc::0000-0002-1496-7816
dc.source.peerreviewno
dc.source.beginpage412
dc.source.endpage415
dc.source.conferenceESSDERC'99 - Proceedings of the 29th European Solid-State Device Research Conference; 13-15 September 1999; Leuven, Belgium.
imec.availabilityPublished - imec


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