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Vertical III-V gate-all-around nanowire MOSFETs: Process integration and contact resistance study

dc.contributor.authorRamesh, Siva
dc.date.accessioned2021-10-29T02:43:53Z
dc.date.available2021-10-29T02:43:53Z
dc.date.issued2020-04
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/35800
dc.sourceIIOimport
dc.titleVertical III-V gate-all-around nanowire MOSFETs: Process integration and contact resistance study
dc.typePHD thesis
dc.contributor.imecauthorRamesh, Siva
dc.contributor.orcidimecRamesh, Siva::0000-0002-8473-7258
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.contributor.thesisadvisorDe Meyer, K.
dc.contributor.thesisadvisorCollaert, Nadine
imec.availabilityPublished - open access


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