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Evaluating latchup (LU) risk in advanced CMOS technologies

dc.contributor.authorSerbulova, Kateryna
dc.contributor.authorGroeseneken, Guido
dc.contributor.authorChen, Shih-Hung
dc.contributor.authorHellings, Geert
dc.date.accessioned2021-10-29T03:55:19Z
dc.date.available2021-10-29T03:55:19Z
dc.date.issued2020
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/35924
dc.sourceIIOimport
dc.titleEvaluating latchup (LU) risk in advanced CMOS technologies
dc.typeMeeting abstract
dc.contributor.imecauthorSerbulova, Kateryna
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.imecauthorChen, Shih-Hung
dc.contributor.imecauthorHellings, Geert
dc.contributor.orcidimecSerbulova, Kateryna::0000-0001-7326-9949
dc.contributor.orcidimecGroeseneken, Guido::0000-0003-3763-2098
dc.contributor.orcidimecHellings, Geert::0000-0002-5376-2119
dc.source.peerreviewyes
dc.source.beginpageC1
dc.source.conferenceInternational ESD Workshop (IEW)
dc.source.conferencedate4/05/2020
dc.source.conferencelocationJesteburg Germany
dc.identifier.urlhttps://www.esda.org/assets/Events/4cf93e2446/IEW-2020-program-1-3-2020.pdf
imec.availabilityPublished - imec


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