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Analysis of the back gate voltage on the LDD SOI NMOSFET series resistance

dc.contributor.authorNicolett, A. S.
dc.contributor.authorMartino, Joao Antonio
dc.contributor.authorSimoen, Eddy
dc.contributor.authorClaeys, C.
dc.date.accessioned2021-10-14T11:31:39Z
dc.date.available2021-10-14T11:31:39Z
dc.date.issued1999
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/3700
dc.sourceIIOimport
dc.titleAnalysis of the back gate voltage on the LDD SOI NMOSFET series resistance
dc.typeOral presentation
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.source.peerreviewno
dc.source.conferenceICMP; August 1999; Campinas, Brazil.
dc.source.conferencelocation
imec.availabilityPublished - imec


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