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Impact of Processing Factors on the Low-Frequency Noise of Gate-All-Around Silicon Vertical Nanowire FETs

dc.contributor.authorSimoen, Eddy
dc.contributor.authorMatagne, Philippe
dc.contributor.authorVeloso, Anabela
dc.contributor.authorClaeys, Cor
dc.date.accessioned2021-10-31T11:13:31Z
dc.date.available2021-10-31T11:13:31Z
dc.date.issued2021
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/37180
dc.sourceIIOimport
dc.titleImpact of Processing Factors on the Low-Frequency Noise of Gate-All-Around Silicon Vertical Nanowire FETs
dc.typeProceedings paper
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.imecauthorMatagne, Philippe
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.source.peerreviewyes
dc.source.beginpage3
dc.source.endpage16
dc.source.conferenceSemiconductor Process Integration 12
dc.source.conferencedate10/10/2021
dc.source.conferencelocationonline online
dc.identifier.urlhttps://doi.org/10.1149/10404.0003ecst
imec.availabilityPublished - imec
imec.internalnotesECS Transactions; Vol. 104; Issue 4


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