NANOWIRE & NANOSHEET FETS FOR ADVANCED ULTRA-SCALED, HIGH-DENSITY LOGIC AND MEMORY APPLICATIONS

Abstract

We report on vertically stacked lateral nanowires (NW) / nanosheets (NS) FETs with a gate-all-around (GAA) configuration as promising candidates to replace finFETs for advanced sub-5nm technology nodes, as they offer higher flexibility to obtain a better power-performance metric for logic applications. Moreover, these devices can be fabricated in a cost effective, co-integration scheme with vertical NW/NS GAA FETs for increased on-chip memory content, thanks to the latter's potential for enabling highly scaled, more energy efficient memory cells, e.g., as the SRAM cell transistors or as the selector for MRAM. Key features and technological challenges for both types of NW/NS FETs will therefore be presented and discussed in this paper.