Device Scaling roadmap and its implications for Logic and Analog platform

Abstract

In the 22nm node, FinFET has been introduced to continue CMOS Logic scaling. The continuous device shrinking needed to reach node 3nm and beyond bring us into the post FinFET era, which requires new device architectures. In this paper we review the device evolution to vertically stacked Nanosheets, Forksheet, and CFET in conjunction with buried power rails and wrap around contact. The impact of variability at scaled dimensions and the requirement for a complete CMOS platform including I/O are discussed. We then review how these elements affect the analog/RF performance of advanced devices in a holistic view.