Comparative Study on the Energy Distribution of Defects under HCD and NBTI in Short Channel p-FinFETs

Abstract

A comparative study is carried out to clarify the energy distribution of traps under hot carrier degradation (HCD) and negative bias temperature instability (NBTI) in short channel p-FinFETs. Two sources of traps, pre-existing traps and generated traps, are identified and their energy profiles are separated using Discharging-based Multi-pulse (DMP) method. The pre-existing traps are located below valance band of silicon (E-v), while the two generated traps are located in 0.4eV above E-v and near conduction band (E-c) of silicon, respectively. The two generated traps are highly sensitive to stress voltage and stress time under NBTI and HCD, however, the generated trap 1 is more sensitive to stress temperature than generated trap 2 under HCD. When switching to long channel devices, the overall degradation is reduced due to less trap generation.