Buried power SRAM DTCO and system-level benchmarking in N3

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dc.contributor.author	Salahuddin, S.
dc.contributor.author	Perumkunnil, M.
dc.contributor.author	Litta, E. Dentoni
dc.contributor.author	Gupta, A.
dc.contributor.author	Weckx, P.
dc.contributor.author	Ryckaert, J.
dc.contributor.author	Na, M. H.
dc.contributor.author	Spessot, A.
dc.date.accessioned	2021-11-02T15:59:09Z
dc.date.available	2021-11-02T15:59:09Z
dc.date.issued	2020
dc.identifier.issn	0743-1562
dc.identifier.other	WOS:000668063000062
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/37745
dc.source	WOS
dc.title	Buried power SRAM DTCO and system-level benchmarking in N3
dc.type	Proceedings paper
dc.contributor.imecauthor	Salahuddin, S.
dc.contributor.imecauthor	Perumkunnil, M.
dc.contributor.imecauthor	Litta, E. Dentoni
dc.contributor.imecauthor	Gupta, A.
dc.contributor.imecauthor	Weckx, P.
dc.contributor.imecauthor	Ryckaert, J.
dc.contributor.imecauthor	Na, M. H.
dc.contributor.imecauthor	Spessot, A.
dc.identifier.eisbn	978-1-7281-6460-1
dc.source.numberofpages	2
dc.source.peerreview	yes
dc.source.conference	IEEE Symposium on VLSI Technology and Circuits
dc.source.conferencedate	JUN 15-19, 2020
imec.availability	Under review

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Version	Item	Date	Summary
2	20.500.12860/37745.2	2021-12-14T09:30:41Z	validation by library/open access desk
1	20.500.12860/37745*	2021-11-02T15:59:09Z