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Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow
dc.contributor.author | Giacomin, Edouard | |
dc.contributor.author | Boemmels, Juergen | |
dc.contributor.author | Ryckaert, Julien | |
dc.contributor.author | Catthoor, Francky | |
dc.contributor.author | Gaillardon, Pierre-Emmanuel | |
dc.date.accessioned | 2021-11-02T16:00:38Z | |
dc.date.available | 2021-11-02T16:00:38Z | |
dc.date.issued | 2020 | |
dc.identifier.issn | 2324-8432 | |
dc.identifier.other | WOS:000658853800007 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/37845 | |
dc.source | WOS | |
dc.title | Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow | |
dc.type | Proceedings paper | |
dc.contributor.imecauthor | Boemmels, Juergen | |
dc.contributor.imecauthor | Ryckaert, Julien | |
dc.contributor.imecauthor | Catthoor, Francky | |
dc.contributor.orcidimec | Catthoor, Francky::0000-0002-3599-8515 | |
dc.identifier.doi | 10.1109/VLSI-SOC46417.2020.9344089 | |
dc.identifier.eisbn | 978-1-7281-5409-1 | |
dc.source.numberofpages | 6 | |
dc.source.peerreview | yes | |
dc.source.beginpage | 34 | |
dc.source.endpage | 39 | |
dc.source.conference | IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC) | |
dc.source.conferencedate | OCT 05-09, 2020 | |
imec.availability | Under review |
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