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Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips
dc.contributor.author | Samavedam, S. B. | |
dc.contributor.author | Ryckaert, J. | |
dc.contributor.author | Beyne, E. | |
dc.contributor.author | Ronse, K. | |
dc.contributor.author | Horiguchi, N. | |
dc.contributor.author | Tokei, Z. | |
dc.contributor.author | Radu, I | |
dc.contributor.author | Bardon, M. G. | |
dc.contributor.author | Na, M. H. | |
dc.contributor.author | Spessot, A. | |
dc.contributor.author | Biesemans, S. | |
dc.date.accessioned | 2021-12-06T02:06:17Z | |
dc.date.available | 2021-12-06T02:06:17Z | |
dc.date.issued | 2020 | |
dc.identifier.issn | 2380-9248 | |
dc.identifier.other | WOS:000717011600132 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/38539 | |
dc.source | WOS | |
dc.title | Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips | |
dc.type | Proceedings paper | |
dc.contributor.imecauthor | Samavedam, S. B. | |
dc.contributor.imecauthor | Ryckaert, J. | |
dc.contributor.imecauthor | Beyne, E. | |
dc.contributor.imecauthor | Ronse, K. | |
dc.contributor.imecauthor | Horiguchi, N. | |
dc.contributor.imecauthor | Tokei, Z. | |
dc.contributor.imecauthor | Radu, I | |
dc.contributor.imecauthor | Bardon, M. G. | |
dc.contributor.imecauthor | Na, M. H. | |
dc.contributor.imecauthor | Spessot, A. | |
dc.contributor.imecauthor | Biesemans, S. | |
dc.identifier.doi | 10.1109/IEDM13553.2020.9372023 | |
dc.identifier.eisbn | 978-1-7281-8888-1 | |
dc.source.numberofpages | 10 | |
dc.source.peerreview | yes | |
dc.source.conference | IEEE International Electron Devices Meeting (IEDM) | |
dc.source.conferencedate | DEC 12-18, 2020 | |
imec.availability | Under review |
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