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dc.contributor.authorSamavedam, S. B.
dc.contributor.authorRyckaert, J.
dc.contributor.authorBeyne, E.
dc.contributor.authorRonse, K.
dc.contributor.authorHoriguchi, N.
dc.contributor.authorTokei, Z.
dc.contributor.authorRadu, I
dc.contributor.authorBardon, M. G.
dc.contributor.authorNa, M. H.
dc.contributor.authorSpessot, A.
dc.contributor.authorBiesemans, S.
dc.date.accessioned2021-12-06T02:06:17Z
dc.date.available2021-12-06T02:06:17Z
dc.date.issued2020
dc.identifier.issn2380-9248
dc.identifier.otherWOS:000717011600132
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/38539
dc.sourceWOS
dc.titleFuture Logic Scaling: Towards Atomic Channels and Deconstructed Chips
dc.typeProceedings paper
dc.contributor.imecauthorSamavedam, S. B.
dc.contributor.imecauthorRyckaert, J.
dc.contributor.imecauthorBeyne, E.
dc.contributor.imecauthorRonse, K.
dc.contributor.imecauthorHoriguchi, N.
dc.contributor.imecauthorTokei, Z.
dc.contributor.imecauthorRadu, I
dc.contributor.imecauthorBardon, M. G.
dc.contributor.imecauthorNa, M. H.
dc.contributor.imecauthorSpessot, A.
dc.contributor.imecauthorBiesemans, S.
dc.identifier.doi10.1109/IEDM13553.2020.9372023
dc.identifier.eisbn978-1-7281-8888-1
dc.source.numberofpages10
dc.source.peerreviewyes
dc.source.conferenceIEEE International Electron Devices Meeting (IEDM)
dc.source.conferencedateDEC 12-18, 2020
imec.availabilityUnder review


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