Buried Bitline for sub-5nm SRAM Design

Abstract

Buried power rail (BPR), i.e., metal wires below the active transistors, has been proposed for routing power and ground lines to improve the performance and density of standard cells and mitigate the increasing RC parasitics at sub-5nm CMOS technology nodes. In this work, we present the Buried Bit-Line (BBL) SRAM technique which utilizes buried metal interconnects for signal routing instead of power or ground routing to achieve better SRAM performance and lower power consumption while requiring minimal process flow changes to the buried power rail technology. Design technology co-optimization (DTCO) is performed using high-accuracy 3D field solvers for parasitic extraction and industry standard techniques to quantify the effect of BBL technology parameters on SRAM circuit metrics. We show that the proposed BBL SRAM can improve access time by up to 11%, write time by up to 31%, and dynamic power by 4%, effectively equivalent to a technology-node gain improvement.