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Buried Bitline for sub-5nm SRAM Design
dc.contributor.author | Mathur, R. | |
dc.contributor.author | Bhargava, M. | |
dc.contributor.author | Salahuddin, S. | |
dc.contributor.author | Schuddinck, P. | |
dc.contributor.author | Ryckaert, J. | |
dc.contributor.author | Annamalai, S. | |
dc.contributor.author | Gupta, A. | |
dc.contributor.author | Chong, Y. K. | |
dc.contributor.author | Sinha, S. | |
dc.contributor.author | Cline, B. | |
dc.contributor.author | Kulkarni, J. P. | |
dc.date.accessioned | 2021-12-06T02:06:50Z | |
dc.date.available | 2021-12-06T02:06:50Z | |
dc.date.issued | 2020 | |
dc.identifier.issn | 2380-9248 | |
dc.identifier.other | WOS:000717011600151 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/38565 | |
dc.source | WOS | |
dc.title | Buried Bitline for sub-5nm SRAM Design | |
dc.type | Proceedings paper | |
dc.contributor.imecauthor | Salahuddin, S. | |
dc.contributor.imecauthor | Schuddinck, P. | |
dc.contributor.imecauthor | Ryckaert, J. | |
dc.contributor.imecauthor | Gupta, A. | |
dc.identifier.doi | 10.1109/IEDM13553.2020.9372042 | |
dc.identifier.eisbn | 978-1-7281-8888-1 | |
dc.source.numberofpages | 4 | |
dc.source.peerreview | yes | |
dc.source.conference | IEEE International Electron Devices Meeting (IEDM) | |
dc.source.conferencedate | DEC 12-18, 2020 | |
imec.availability | Under review |
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