Screening of 193i and EUV lithography process options for STT-MRAM orthogonal array MTJ pillars

Abstract

Spin-transfer torque magnetic random-access memory (STT-MRAM) is considered as the most promising candidate to replace the complementary metal-oxide-semiconductor (CMOS) based memories that are dominating the market in the last few decades. What makes STT-MRAM superior to other memories is the high read and write speeds, non-volatility, good cycling endurance and near-zero leakage. Moreover, with the perpendicular device topology and the single transistor cell configuration, it becomes a very promising candidate for further device scaling which is essential to increase the memory densities. This paper focuses on the experiments performed using different lithography approaches in order to explore the smallest printable pitches for orthogonal array magnetic tunnel junction (MTJ) pillars, which are the main components of the STT-MRAM. Considering the high impact of the MTJ patterning process on the robustness of the memory device, several post-litho performance parameters such as wafer critical dimension uniformity (WCDU), local critical dimension uniformity (LCDU) and pillar circularity have also been measured and compared.