A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability

Abstract

The power consumption of modern highly complex chips during scan test is significantly higher than the power consumed during functional mode. This leads to substantial heat dissipation, excessive IR drop, and unrealistic timing failures of the integrated circuits (ICs) under test. In this brief, a ByPassable Scan Data Retention Flip-Flop (BPS-DRFF) is proposed for low-power IC test. The proposed flip-flop contains two secondary latches. The output of the "function" secondary latch goes to the following combinational circuits, while the other "shadow" secondary latch is used to shift test vectors during scan test. By gating the output of the function secondary latch, the redundant switching activity in the combinational circuits is eliminated during scan shift, thereby reducing the test power consumption significantly. The suppressed switching activity also leads to lower IR drop across the chip, increasing the chip manufacturing yield. Furthermore, the shadow latch is reused for data retention in the sleep mode while performing power gating, thereby alleviating the area cost of the shadow latch. The proposed BPS-DRFF also eases the hold time sign-off in the test mode due to the elongated clock-to-Q contamination delay that is brought in by the shadow latch. The proposed design is applied to an AES-128 crypto core in a UMC 55-nm low power CMOS technology. Experiment results show that 68.5% power is saved during scan test with the proposed BPS-DRFF, compared to the standard scan retention flip-flop.