3D sequential CMOS top tier devices demonstration using a low temperature Smart Cu (TM) Si layer transfer

Abstract

A low temperature Smart Cu (TM) process was used to fabricate SOI substrates, suitable for 3D sequential device stacking. Electrical performance of FDSOI planar devices fabricated on such low temperature SOI substrate was compared to devices fabricated on a reference high temperature SOI wafer. Electrical parameters (V-T, SS, DIBL, BTI) of the devices closely match for the two substrates, while a small degradation of the electron and hole carrier mobility is observed in the low temperature substrate. Additional thermal steps during processing, such as spike anneal, or after processing, such as FGA, did not have a significant impact on the carrier mobility.