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Program charge interference and mitigation in vertically scaled single and multiple-channel 3D NAND flash memory

dc.contributor.authorVerreck, Devin
dc.contributor.authorArreghini, Antonio
dc.contributor.authorVan den Bosch, Geert
dc.contributor.authorFurnemont, Arnaud
dc.contributor.authorRosmeulen, Maarten
dc.date.accessioned2022-04-04T10:04:36Z
dc.date.available2022-04-04T02:09:03Z
dc.date.available2022-04-04T10:04:36Z
dc.date.issued2021
dc.identifier.issn1946-1569
dc.identifier.otherWOS:000766985400064
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/39569.2
dc.sourceWOS
dc.titleProgram charge interference and mitigation in vertically scaled single and multiple-channel 3D NAND flash memory
dc.typeProceedings paper
dc.contributor.imecauthorVerreck, Devin
dc.contributor.imecauthorArreghini, Antonio
dc.contributor.imecauthorVan den Bosch, Geert
dc.contributor.imecauthorFurnemont, Arnaud
dc.contributor.imecauthorRosmeulen, Maarten
dc.contributor.orcidimecVerreck, Devin::0000-0002-3833-5880
dc.contributor.orcidimecArreghini, Antonio::0000-0002-7493-9681
dc.contributor.orcidimecVan den Bosch, Geert::0000-0001-9971-6954
dc.contributor.orcidimecFurnemont, Arnaud::0000-0002-6378-1030
dc.contributor.orcidimecRosmeulen, Maarten::0000-0002-3663-7439
dc.identifier.doi10.1109/SISPAD54002.2021.9592552
dc.identifier.eisbn978-1-6654-0685-7
dc.source.numberofpages4
dc.source.peerreviewyes
dc.source.beginpage272
dc.source.endpage275
dc.source.conferenceInternational Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
dc.source.conferencedateSEP 27-29, 2021
dc.source.conferencelocationDallas
dc.source.journalna
imec.availabilityPublished - imec


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220.500.12860/39569.2*2022-04-04T10:02:07Zvalidation by library/open access desk
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