Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner- spacers and Epi-induced Stress: Understanding & Mitigating Process Risks

Abstract

This paper benchmark the intrinsic trade-off between two essential modules of gate-all-around GAA nanosheet (NS)FETs viz. inner-spacers (ISPs) epi-induced stress in the channel. While having both ISPs and the stress is the best-case scenario for NSFET, it comes with enhanced process challenges and performance risks: poor epi-quality resulting in a no-channel stress scenario. While inner-spacers are important to parasitic capacitance reduction, we show that having intrinsic epi-stress is more beneficial and provides a better performance trade-off. We further evaluate the impact of inner-spacer x-value and enhanced epi-volume for the two different cases. Finally, we have performed self-heating studies to show how skipping inner-spacers can provide additional reduction in peak temperature.