An Efficient Reconfigurable Neural Network on Chip

Abstract

Neural networks are being used in several domains and applications. One of the main challenges is the hardware implementation of neural networks. The hardware design is fixed in the number of nodes and layers that make the network applicable to specific applications. This paper presents a reconfigurable neural network where the number of layers and nodes can be changed according to the applications. The proposed method is based on the Network on Chip (NoC) configuration, which is used for routing data between different layers and nodes. Each router in NoC is connected to m nodes that can represent a part or complete layer. According to the reconfiguration, the number of routers can be selected to present each layer, and the number of needed nodes per layer is decided by the number of nodes in each router. The proposed method is implemented on FPGA Altera 10 GX, and it achieves an accuracy of 97% for using the MNIST dataset. The throughput and delay of the proposed method are more efficient compared to the traditional method.