An Efficient Embryonic Hardware Architecture based on Network-on-Chip

Abstract

Embryonic Hardware (EmHW) is commonly used in several domains due to its ability to self-heal and reconfigure itself as needed. The main challenges of the current EmHW method are high average delay and low throughput. This paper proposes an efficient EmHW approach based on Network-on-Chip (NoC) to improve system performance. In the proposed method, EmHW consists of multiple cells, and the proposed cell has better performance than the traditional EmHW cell. The NoC is used to provide flexible communication between the cells. The proposed method is implemented and tested using VHDL on Altera Arria 10 GX FPGA. The proposed method improves the throughput by up to 92% and decreases average delay by up to 80% at a small area overhead. The method is tested using multiple traffic patterns, and the results show the effectiveness and viability of the proposed method for both delay and throughput.