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A compact MOSFET breakdown model for optimization of gate coupled ESD protection circuits

dc.contributor.authorVassilev, Vesselin
dc.contributor.authorGroeseneken, Guido
dc.contributor.authorBock, Karlheinz
dc.contributor.authorMaes, Herman
dc.date.accessioned2021-10-14T11:53:09Z
dc.date.available2021-10-14T11:53:09Z
dc.date.issued1999
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/3985
dc.sourceIIOimport
dc.titleA compact MOSFET breakdown model for optimization of gate coupled ESD protection circuits
dc.typeProceedings paper
dc.contributor.imecauthorGroeseneken, Guido
dc.source.peerreviewno
dc.source.beginpage600
dc.source.endpage603
dc.source.conferenceESSDERC'99 - Proceedings of the 29th European Solid-State Device Research Conference; 13-15 September 1999; Leuven, Belgium.
dc.source.conferencelocation
imec.availabilityPublished - imec


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