Browsing Conference contributions by imec author "af0a0bbd0d9f2fad7128b94b6104887578ac8653"
Now showing items 1-5 of 5
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Extreme scaling enabled by MX2 transistors: variability challenges (invited)
Smets, Quentin; Arutchelvan, Goutham; Schram, Tom; Verreck, Devin; Groven, Benjamin; Cott, Daire; Ahmed, Zubair; Shi, Yuanyuan; Sutar, Surajit; Nalin Mehta, Ankit; Lin, Dennis; Asselberghs, Inge; Radu, Iuliana (2021) -
From Design to System-Technology optimization for CMOS
Ryckaert, Julien; Chehab, Bilal; Jang, Doyoung; Mirabelli, Gioele; Salahuddin, Shairfe Muhammad; Schuddinck, Pieter; Zografos, Odysseas; Ahmed, Zubair; Weckx, Pieter; Hellings, Geert (2021) -
Introducing 2D-FETs in Device Scaling Roadmap using DTCO
Ahmed, Zubair; Afzalian, Aryan; Schram, Tom; Jang, Doyoung; Verreck, Devin; Smets, Quentin; Schuddinck, Pieter; Chehab, Bilal; Sutar, Surajit; Arutchelvan, Goutham; Soussou, Assawer; Asselberghs, Inge; Spessot, Alessio; Radu, Iuliana; Parvais, Bertrand; Ryckaert, Julien; Na, Myung Hee (2020) -
Scaling of double-gated WS2 FETs to sub-5nm physical gate length fabricated in a 300mm FAB
Smets, Quentin; Schram, Tom; Verreck, Devin; Cott, Daire; Groven, Benjamin; Ahmed, Zubair; Kaczer, Ben; Mitard, Jerome; Wu, Xiangyu; Kundu, Souvik; Mertens, Hans; Radisic, Dunja; Thiam, Arame; Li, Waikin; Dupuy, Emmanuel; Tao, Zheng; Vandersmissen, Kevin; Maurice, Thibaut; Lin, Dennis; Morin, Pierre; Asselberghs, Inge; Radu, Iuliana (2021) -
Two-level MOL and VHV routing style to enable extreme height scaling beyond 2nm technology node
Chehab, Bilal; Zografos, Odysseas; Dentoni Litta, Eugenio; Ahmed, Zubair; Schuddinck, Pieter; Jang, Doyoung; Hellings, Geert; Spessot, Alessio; Weckx, Pieter; Ryckaert, Julien (2021)