Browsing Conference contributions by author "Facchini, Marco"
Now showing items 1-4 of 4
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3D IO interface design between memory and logic dies on TSV interconnects
Facchini, Marco; Marchal, Pol; Dehaene, Wim (2009) -
An RDL-configurable 3D memory tier to replace on-chip SRAM
Facchini, Marco; Marchal, Pol; Catthoor, Francky; Dehaene, Wim (2010) -
Stackable memory of 3D chip integration for mobile applications
Gu, S.Q.; Marchal, Pol; Facchini, Marco; Wang, F.; Suh, M.; Lisk, D.; Nowak, M. (2008) -
System-level power/performance evaluation of 3D stacked DRAMs for mobile applications
Facchini, Marco; Carlson, Trevor; Vignon, Anselme; Palkovic, Martin; Catthoor, Francky; Dehaene, Wim; Benini, Luca; Marchal, Pol (2009)