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Extended Scale Length Theory Targeting Low-Dimensional FETs for Carbon Nanotube FET Digital Logic Design-Technology Co-optimization
dc.contributor.author | Gilardi, C. | |
dc.contributor.author | Chehab, B. | |
dc.contributor.author | Sisto, G. | |
dc.contributor.author | Schuddinck, P. | |
dc.contributor.author | Ahmed, Z. | |
dc.contributor.author | Zografos, O. | |
dc.contributor.author | Lin, Q. | |
dc.contributor.author | Hellings, G. | |
dc.contributor.author | Ryckaert, J. | |
dc.contributor.author | Wong, H-S P. | |
dc.contributor.author | Mitra, S. | |
dc.date.accessioned | 2022-07-09T02:28:02Z | |
dc.date.available | 2022-07-09T02:28:02Z | |
dc.date.issued | 2021 | |
dc.identifier.issn | 2380-9248 | |
dc.identifier.other | WOS:000812325400173 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/40094 | |
dc.source | WOS | |
dc.title | Extended Scale Length Theory Targeting Low-Dimensional FETs for Carbon Nanotube FET Digital Logic Design-Technology Co-optimization | |
dc.type | Proceedings paper | |
dc.contributor.imecauthor | Chehab, B. | |
dc.contributor.imecauthor | Sisto, G. | |
dc.contributor.imecauthor | Schuddinck, P. | |
dc.contributor.imecauthor | Ahmed, Z. | |
dc.contributor.imecauthor | Zografos, O. | |
dc.contributor.imecauthor | Hellings, G. | |
dc.contributor.imecauthor | Ryckaert, J. | |
dc.identifier.doi | 10.1109/IEDM19574.2021.9720672 | |
dc.identifier.eisbn | 978-1-6654-2572-8 | |
dc.source.numberofpages | 4 | |
dc.source.peerreview | yes | |
dc.source.conference | IEEE International Electron Devices Meeting (IEDM) | |
dc.source.conferencedate | DEC 11-16, 2021 | |
dc.source.conferencelocation | San Francisco | |
imec.availability | Under review |
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