Beyond-Cu Intermediate-Length Interconnect Exploration for SRAM Application

Abstract

Promising interconnect materials continue to emerge and are considered as potential replacements for Cu interconnects. In this paper, an intermediate-length interconnect technology exploration framework for SRAM array-level performance based on CACTI 7 is presented to efficiently optimize various emerging interconnect technologies. Three graphene-based wire materials are benchmarked against their traditional Cu counterpart for optimal SRAM array-level performance. Furthermore, we investigate the scalability of the emerging wire for the SRAM application under five technology nodes based on ASU Predictive Technology Model for FinFET devices and quantify the impact of different cache sizes on key performance metrics, including energy-delay product (EDP) and energy-delay-area product (EDAP). Results demonstrate that the cache using thick graphene wires has over 19% EDP reduction comparing the Cu counterpart. It is shown that up to 37% of the EDAP improvement can be achieved by thick graphene wires for 2MB cache size at 7 nm.