EUV based multi-patterning schemes for advanced DRAM nodes

Abstract

The new generation of 10nm node DRAM devices have now adopted EUV based patterning techniques. With further shrink in design rules, single exposure EUV processes will be pushed further using advanced photoresists and new mask types. However, in absence of high NA EUV lithography ready for high volume manufacturing (HVM) until at least 2025, acceptable local CD (critical dimensions) uniformity and yielding process windows at low exposure dose are a challenge for single exposure EUV. Further, for EUV implementation in sub-32nm pitch DRAM capacitator patterning applications, multi-patterning techniques must be explored.

In this paper, EUV based double-patterning techniques have been demonstrated to pattern honeycomb array contact holes and pillars. The processing utilizes two EUV masks, using simple angled line space patterns. We have explored two different types of double patterning options: litho-freeze-litho-etch (LFLE) to pattern contact holes and litho-etch-litho-etch (LELE) to pattern pillars. In the absence of high NA EUV, these processing techniques are useful to pattern tight pitch (e.g., 32nm) contact holes/pillars for newer generations of DRAM devices. Another key objective of this paper is to present a set of metrology characterization methods to enable proper process optimizations.