Orthogonal Array Pillar Process Development for High Density 4F2 Memory Cells at 40nm Pitch and Beyond

Abstract

The use of a 4F(2) cell configuration which enables higher densification is common in emerging memory devices. The pitch scaling and the robustness of these devices mainly rely on the patterning of the orthogonal array vertical pillar process. In this paper, we screen several lithography process approaches to optimize the 40nm pitch pillar patterning using single exposure EUV (extreme ultraviolet) lithography. The results show that with the optimized 40nm pitch process roughly 0.6nm 3-Sigma WCDU (wafer critical dimension uniformity) and 1.4nm 3-Sigma LCDU (local critical dimension uniformity) can be obtained post-litho for 21.1mn mean CD (critical dimension). Post-etch patterning with the best process shows 1.8nm 3-Sigma WCDU and 1.3nm 3-Sigma LCDU at 17.2nm mean CD. Smaller pitches have also been explored to identify the limits of the single EUV lithography process. Structures at 34nm pitch have shown high amount of pillar collapse. For 36nm pitch, on the other hand, a reasonable litho performance could be obtained with slightly boosted CD. The post-litho results show that with the optimized 36nm pitch process 0.4nm 3-Sigma WCDU and 1.4nm 3-Sigma LCDU can be obtained for 19.1nm mean CD.