Adaptive Hardware Architecture for Neural-Network-on-Chip

Abstract

Neural networks are beneficial for several applications in classification and regression problems. Hardware implementation of a neural network is a challenge in terms of making adaptive architecture to fit different applications. Network-on-Chip (NoC) is an efficient method in power and bandwidth to make communication between several nodes. This paper proposes an adaptive neural network based on NoC. NoC consists of routers and Process Elements (PEs), and each router is connected to its PE which consists of m nodes. These nodes are used to construct layers for a neural network. A configuration packet is used to show the number of layers and of nodes per layer. The proposed method can assign multiple routers to represent a layer based on the required configuration. Thus, the proposed method supports the construction of different layers with the adaptability of different nodes configuration (desired number) appropriate for the target application. The proposed method is implemented on FPGA Altera 10 GX, and it achieves an accuracy of 98.18% with the MNIST dataset. It has been also tested using multiple datasets. The results show the proposed method has comparable resource utilization with the traditional method.